View IRMCF188TY_8801901.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

irmcf188 1 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 high performance sensorless motor control ic description irmcf188 is a high performance flash based motion control ic designed and optimized for complete ai r conditioner control which contains two computation engines integrated into one monolithic chip. one is the flexible motion control engine (mce tm ) for sensorless control of permanent magnet motors or induction motors; the other is an 8 - bit high - speed microcontroller (8051). th e user can program a motion control algorithm by connecting these control elements using a graphic compiler. key components of the complex sensorless control algorithms, such as the angle estimator, are provided as complete pre - defined control blocks. a un ique analog/digital circuit and algorithm fully support s single shunt or leg shunt current reconstruction. irmcf188 performs a pfc (power factor correction) function in addition to the m otor control. irmcf188 comes in a 64 pin qfp package . features ? mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? built - in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits ? supports induction machine and both interior and surface permanent magnet motor sensorless control ? dedicated pfc pwm for digital pfc control ? loss minimization space vector pwm ? three - channel analog output (pwm) ? embedded 8 - bit high speed microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for emulation/debugger ? serial communication interface (uart) ? i2c/spi serial interface ? three general purpose timers/counters ? two special timers: periodic timer, capture ti mer ? watchdog timer with independent internal clock ? internal 64 kbyte flash memory ? 3.3v single supply product summary maximum clock input (f crystal ) 60 mhz maximum internal clock (sysclk) 120mhz maximum 8051 clock (8051clk) 30mhz mce tm computation data rang e 16 bit signed 8051 program flash 52kb 805 1 /mce data ram 4kb mce program ram 12 kb gatekill latency (digital filtered) 2 sec pwm carrier frequency 20 bits/ sys clk a/d input channels 10 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6 k bps number of digital i/o (max) 24 package (lead free) qfp64 typical 3.3v operating current 30 ma base part number package type standard pack orderable part number form quantity irmcf1 88 lqfp64 tape and reel 1500 irmcf1 88tr irmcf1 88 lqfp64 tray 1600 irmcf1 88ty downloaded from: http:///
irmcf188 2 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 table of contents 1 overview ................................................................................................................................ 5 2 pinout ..................................................................................................................................... 6 3 irmcf188 block diagram and main functions ..................................................................... 7 4 application connection and pin function ................................................................................. 9 4.1 8051 peripheral interface group .......................................................................................... 10 4.2 motion peripheral interface group ....................................................................................... 11 4.3 analog interface group ........................................................................................................ 12 4.4 power interface group ......................................................................................................... 12 4.5 test interface group ............................................................................................................ 12 5 dc characteristics ............................................................................................................... 14 5.1 absolute maximum ratings .................................................................................................. 14 5.2 system clock frequency and power consumption ............................................................. 14 5.3 digital i/o dc characteristics ............................................................................................... 15 5.4 analog i/o dc characteristics ............................................................................................. 16 5.5 under voltage lockout dc characteristics ........................................................................... 17 5.6 itrip comparator dc characteristics ...................................................................................... 17 5.7 cmext and aref characteristics ...................................................................................... 17 6 ac characteristics ................................................................................................................ 18 6.1 digital pll ac characteristics ............................................................................................. 18 6.2 analog to digital converter ac characteristics .................................................................... 19 6.3 op amp ac characteristics .................................................................................................. 20 6.4 sync to svpwm and a/d conversion ac timing .............................................................. 21 6.5 gatekill to svpwm ac timing ........................................................................................ 22 6.6 itrip ac timing ...................................................................................................................... 22 6.7 interrupt ac timing .............................................................................................................. 23 6.8 i2c ac timing ...................................................................................................................... 24 6.9 spi ac timing ...................................................................................................................... 25 6.10 uart ac timing ................................................................................................................ 27 6.11 capture input ac timing ................................................................................................ 28 6.12 jtag ac timing ................................................................................................................. 29 7 i/o structure ......................................................................................................................... 30 8 pin list .................................................................................................................................. 34 9 package dimensions ............................................................................................................ 36 10 part marking information ...................................................................................................... 37 11 qualification information ....................................................................................................... 37 downloaded from: http:///
irmcf188 3 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 list of tables table 1. analog channel sensing functions in leg and single shunt modes ........................... 12 table 2. absolute maximum ratings ....................................................................................... 14 table 3. system clock frequency ........................................................................................... 14 table 4. digital i/o dc characteristics .................................................................................... 15 table 6. analog i/o dc characteristics ................................................................................... 16 table 7. uvcc dc characteristics ........................................................................................... 17 table 8. itrip dc characteristics .............................................................................................. 17 table 9. cmext and aref dc characteristics ...................................................................... 17 table 10. pll ac characteristics ............................................................................................ 18 table 11 . a/d converter ac characteristics .......................................................................... 19 table 12 current sensing op amp ac characteristics ........................................................... 20 table 13. sync ac characteristics ........................................................................................ 21 table 14. gatekill to svpwm ac timing ........................................................................... 22 table 15. itrip ac timing ......................................................................................................... 22 table 16. interrupt ac timing .................................................................................................. 23 table 17. i 2 c ac timing ......................................................................................................... 24 table 18. spi write ac timing ................................................................................................ 25 table 19. spi read ac timing ................................................................................................ 26 table 20. uart ac timing ..................................................................................................... 27 table 21. capture ac timing .............................................................................................. 28 table 22. jtag ac timing ...................................................................................................... 29 table 23. pin list ..................................................................................................................... 35 downloaded from: http:///
irmcf188 4 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 list of figures figure 1. typical application block diagram using irmcf188 ................................................... ............................. 5 figure 2. pinout of irmcf188 ................................................... ................................................... ............................. 6 figure 3. irmcf188 block diagram ................................................... ................................................... .................... 7 figure 4. irmcf188 leg shunt connection diagram ................................................... ............................................ 9 figure 5. irmcf188 single shunt connection diagram ................................................... ...................................... 10 figure 6. crystal circuit example ................................................... ................................................... ....................... 18 figure 7. voltage droop and s/h hold time ................................................... ................................................... ....... 19 figure 8 op amp output capacitor ................................................... ................................................... ..................... 20 figure 9. sync timing ................................................... ................................................... ....................................... 21 figure 10. gatekill timing ................................................... ................................................... ................................... 22 figure 11. itrip timing ................................................... ................................................... ...................................... 22 figure 12. interrupt timing ................................................... ................................................... ................................. 23 figure 13. i 2 c timing ................................................... ................................................... ......................................... 24 figure 14. spi write timing ................................................... ................................................... ................................ 25 figure 15. spi read timing ................................................... ................................................... ................................. 26 figure 16. uart timing ................................................... ................................................... ..................................... 27 figure 17. capture timing ................................................... ................................................... .............................. 28 figure 18. jtag timing ................................................... ................................................... ...................................... 29 figure 19. pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh output ................................................... ......... 30 figure 20. all digital i/o except motor pwm output ................................................... ............................................. 30 figure 21. reset, gatekill i/o ................................................... ................................................... .................... 31 figure 22. analog input ................................................... ................................................... ..................................... 31 figure 23. adcl pin input structure ................................................... ................................................... .................. 31 figure 24 analog operational amplifier output and aref i/o structure ................................................... ............. . 32 figure 25. vss,avss pin i/o structure ................................................... ................................................... ............. 32 figure 26. vdd1,vddcap pin i/o structure ................................................... ................................................... ..... 32 figure 27. xtal0/xtal1 pins structure ................................................... ................................................... ............ 33 downloaded from: http:///
irmcf188 5 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 1 overview irmcf188 is a new generation international rectifier integrated circuit device primarily designed as a one - chip solution for complete inverter ized appliance motor control applications. unlike a traditional microcontroller or dsp, the irmcf188 provides a built - in closed loop sensorless control algorithm using the unique flexible motion control engine (mce tm ) for permanent magnet motors as well as induction motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmcf188 also employs a unique single shunt current reconstruction c ircuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor inte rface to the ic, while still supporting leg shunt current sensing. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high - speed 8 - bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging. figure 1 shows a typical application schematic using the irmcf188 in leg shunt mode. irmcf188 contains 64k bytes of flash program memory and comes in a 64 - pin qfp package. irmcf188 power supply irs2630d digial i/o appliance inverter with pfc 3.3v passive emi filter host communication motor (pmsm or im) galvanic isolation analog input 22 6 2 pfc gate drive uart interface to front panel figure 1 . typical application block diagram using irmcf188 downloaded from: http:///
irmcf188 6 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 2 pinout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 1316 3 12 4 11 56 7 8 9 10 2 1 p1.1/rxd p1.2/txd vdd1 vss vddcap p1.3/sync/sck p1.4/cap p3.2/int0 34 35 3633 4637 4538 4443 42 41 40 39 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ain2 op1o vdcbus p2.7/aopwm1 p2.6/aopwm0 pwmuh pwmvhpwmwh pwmul pwmvl pwmwl gatekill vdd1 vss op2o op2- op2+ xtal0 t3.5/t1reset p1.5 tcktdi/p5.1 tdo/p5.3 tms/p5.2 sda/cs0 scl/sdi-sdo pfcgkillpfcpwm p2.1 irmcf188 (top view) ain4 ain3 op3oop3+ op3- p2.0/nmi p2.2 ain1 p3.3/int1 p1.7 p1.6 p1.0/t2 p3.1/aopwm2 p3.0/cs1 xtal1 p2.3 op1- op1+ vddcap t3.4/t0 avss aref cmext p3.7 adch adcl figure 2 . pinout of irmcf188 downloaded from: http:///
irmcf188 7 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 3 irmcf188 block diagram and main functions irmcf188 block diagram for leg shunt mode is shown in figure 3 . motion control sequencer dual port ram 2 kbyte mce program ram 12kbyte program flash 64kb 8bit up address/data bus motion control bus s/h a/d mux d/a ( pwm) timer counnter0,1,2 watchdog timer motion control modules uart i2c sndrcv 6 low loss svpwm vdcbus gatekill to igbt gate drive mini- motion control engine ( minimce) monitoring host interface digital i/os 8 bit ( 8051) microcontroller ain1ain2 jtag emulator debugger 4 freq synthesizer 2 ceramic resonator (4mhz) 30mhz ain3 analog input 2 capture interrupt control motor current reconstruct speed command port 1 scl sda port 2 port 3 ain4 pfc pwm pfc current sense 8bit cpu core local ram 2 kbyte 120mhz op2 op3 op1 3 3 3 adch adcl gatekill to igbt gate drive figure 3 . irmcf188 block diagram irmcf188 contains the following functions for sensorless ac motor control applications: motion control engine (mce tm ) ? sensorless foc (complete sensorless field oriented control) ? proportional plus integral block ? low pass filter ? differentiator and lag (high pass filter) ? ramp ? limit ? angle estimate (sensorless control) ? inverse clark transformation ? vector rotator ? bit latch ? peak detect ? transition ? multiply - divide (signed and unsigned) ? adder 8051 microcontroller ? two 16 bit timer/counters ? one 16 bit periodic timer ? one 16 bit watchdog timer ? one 16 bit capture timer ? up to 2 4 discrete digital i /os ? ten- channel 12 bit a/d o buffered (current sensing) three channels (0 C 1.2v input) o unbuffered seven channels (0 C 1.2v inpu t) ? jtag port (4 pins) ? up to three channels of analog output (8 bit pwm) ? uart ? i 2 c/spi port downloaded from: http:///
irmcf188 8 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 ? divide (signed and unsigned) ? subtractor ? comparator ? counter ? accumulator ? switch ? shift ? atan (arc tangent) ? function block (any curve fitting, nonlinear function) ? 16 bit wide logic operations (and, or, xor, not, negate) ? mce tm program memory and dual port ram (6k byte) ? mce tm control sequencer ? 64k byte flash memory ? 2k byte data ram downloaded from: http:///
irmcf188 9 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 4 application connection and pin function figure 4 shows the application connections in leg shunt mode. figure 5 shows the application connections in single shunt mode. p1.2/ txd p1.1/ rxd xtal0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ain2 C ain4 host microcontroller (rs232c) digital i/o control system clock 4 mhz crystal p2.6/ aopwm0 analog output xtal1 p3.0/int2 reset tdi jtag control ( otp programming & emulation) t clk tsm tdo 0.6v op2+ op2- - op2o other analog input (0 C 1,2v) avdd 1.8v avss vdd1 3.3v vss cmext op3+ op3- - op3o op1+ op1- - op1o optional external voltage reference (0.6v) p2.7/ aopwm1 scl sda other communication (i 2 c) frequency synthesizer rs232c i 2 c/spi port1 port2 reset pwm0 pwm1 jtag interface low loss space vector pwm s/h 8051 cpu dual port memory (2kb) & mce memory (12kb) motion control modules motion control sequencer 12-bit a/d & mux system clock local ram (2 kbyte) program flash (64 kbyte) system reset watchdog timer timers irmcf188 aref pwm2 p3.1/ aopwm2 port3 p1.5 p1.6 p1.7 p2.2 p2.0/ nmi p2.3 p3.2/ int0 3 1.8v voltage regulator vddcap 3.3v motor shunt resistors p3.3 p3.4 p3.5 p2.1 motor hvic gate drive irs2336d 0.6v motor current reconstruct 0.2v from pfc shunt ac 230v pfcpwm pfc gatekill pfc shunt resistor p1.3/sync p1.0/t2 p1.4/cap s/h adch, adcl 2 a/d calibration reference voltages from ac voltage vdcbus vac+ vac- vaco 0.2v ain1 figure 4 . irmcf188 leg shunt connection diagram downloaded from: http:///
irmcf188 10 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 p1.2/ txd p1.1/ rxd xtal0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ain1 C ain4 host microcontroller (rs232c) digital i/o control system clock 4 mhz crystal p2.6/ aopwm0 analog output xtal1 p3.0/int2 reset tdi jtag control ( otp programming & emulation) t clk tsm tdo 0.6v op2+ op2- op2o other analog input (0 C 1,2v) avdd 1.8v avss vdd1 3.3v vss cmext op3+ op3- op3o op1+ op1- op1o optional external voltage reference (0.6v) p2.7/ aopwm1 scl sda other communication (i 2 c) frequency synthesizer rs232c i 2 c/spi port1 port2 reset pwm0 pwm1 jtag interface low loss space vector pwm s/h 8051 cpu dual port memory (2kb) & mce memory (12kb) motion control modules motion control sequencer 12-bit a/d & mux system clock local ram (2 kbyte) program flash (64 kbyte) system reset watchdog timer timers irmcf188 aref pwm2 p3.1/ aopwm2 port3 p1.6 p1.7 p2.2 p2.0/ nmi p2.3 p3.2/ int0 4 3.3v 1.8v voltage regulator vddcap 3.3v motor shunt resistor p3.3 p3.4 p3.5 p2.1 motor hvic gate drive irs2336d 0.6v motor current reconstruct 0.2v from pfc shunt ac 230v pfcpwm pfc gatekill pfc shunt resistor p1.3/sync p1.0/t2 p1.4/cap s/h adch, adcl 2 a/d calibration reference voltages from ac voltage vdcbus p1.5 figure 5. irmcf188 single shunt connection diagram 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from irmc f188 p1.1/rxd input, receive data to irmc f188 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer/counter 2 input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output p1.4/cap input/o utput port 1.4, can be configured as capture timer input p1.5 input/output port 1.5 p1.6 input/output port 1.6 p1.7 input/output port 1.6 p2.0/nmi input/output port 2.0, can be configured as non - maskable interrupt input p2.2 input/output port 2.2 p2.3 inpu t/output port 2.3 p2.6/aopwm0 input/output port 2.6, can be configured as aopwm0 output downloaded from: http:///
irmcf188 11 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 p2.7/aopwm1 input/output port 2.7, can be configured as aopwm1 output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 p3.1/aop wm2 input/output port 3.1, can be configured as aopwm2 output p3.2/nint0 input/output port 3.2, can be configured as int0 input p3.3/nint1 input/output port 3.3, can be configured as int1 input p3.4/t0 input/output port 3.4, can be configured as t0 input for counter mode p3.5/t1 input/output port 3.5, can be configured as t1 input for counter mode p3.7 input/output port 3.7 p5.1/tdi input port 5.1, configured as jtag port by default p5.2/tms input port 5.2 , configured as jtag port by default analog output interface p2.6/aopwm0 input/output, can be configured as 8 - bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8 - bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configure d as 8 - bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesnt require external rc time constant i 2 c interface scl/so - si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 i 2 c/spi interface scl/so - si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal, in ternally pulled down by 58k?, configured high true at a power up pwmul output, pwm phase u low side gate signal, internally pulled down by 58k?, configured high true at a power up pwmvh output, pwm phase v high side gate signal, internally pulled down by 5 8k?, configured high true at a power up pwmvl output, pwm phase v low side gate signal, internally pulled down by 58k?, configured high true at a power up pwmwh output, pwm phase w high side gate signal, internally pulled down by 58k?, configured high true at a power up pwmwl output, pwm phase w low side gate signal, internally pulled down by 58k?, configured high true at a power up pfcpwm output, pfcpwm output signal, internally pulled up by 70k?, configured low t rue at a power up downloaded from: http:///
irmcf188 12 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 fault gatekill input, u pon assertion this negates all six pwm signals, active low, internally pulled up by 70k? pfcgkill input, upon assertion, this negates pfcpwm signal, active low, internally pul led up by 70k? 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. op1+ input, operational amplifier positive input for application sensing op1 - input, operational amplifier negative input for application sensing op1o output, operational amplifier output for application sensing op2+ input, operational amplifier positive input for application sensing op2 - input, operational amplifier negative input for application sensing op2o output, operational amplifier output for application sensing op3+ input, operational amplifier positive input for application sensing op3 - input, operational amplifier negative input for application sensing op3o output, operational amplifier output for a pplication sensing vdcbus input, analog input channel (0 C 1.2v), allocated for dc bus voltage input ain1 input, analog input channel 1 (0 C 1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0 C 1.2v), needs to be pulled down to avss if unused ain3 input, analog input channel 3 (0 C 1.2v), needs to be pulled down to avss if unused ain4 input, analog input channel 4 (0 C 1.2v), needs to be pulled down to avss if unused a dch input, analog input channel dedicated for a/d com pensation (0 C 1.2v) , needs to be pulled down to avss if unused adcl input, analog input channel dedicated for a/d compensation (0 C 1.2v), internally biased to 0.6v, see figure 23 for internal structure analog channel leg shunt mode single shunt mode pin number(s) op1 pfc current ac voltage 19, 20, 21 op2 motor u phase current motor shunt current 28, 29, 30 op3 motor v phase current pfc current 34, 35, 36 ain1 ac voltage unallocated 23 table 1 . analog channel sensing functions in leg and single shunt modes 4.4 power interface group vdd1 digital power (3.3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not designed to power any external circuits or devices. only capacitors should be connected to this pin. vss digital common 4.5 test interface group p5.2/tms jtag test mode input or input digital port downloaded from: http:///
irmcf188 13 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 tdo jtag data output p5.1/tdi jtag data input, or input digital port tck jtag test clock downloaded from: http:///
irmcf188 14 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 6.0 v respect to vss t a ambient temperature - 40 ?c - 85 ?c t s storage temperature - 65 ?c - 150 ?c table 2 . absolute maximum ratings caution: stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditi ons beyond those indicated in the operational sections of the specifications are not implied. 5.2 system clock frequency and power consumption c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max unit sysclk system clock 32 - 120 mhz p d power consumption 100 1) - mw table 3 . system clock frequency note 1) the value is based on the condition of mce clock=1 0 0mhz, 8051 clock 20 mhz with a actual motor and pfc running by a typical mce application program and 8051 code. downloaded from: http:///
irmcf188 15 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v il input low voltage - 0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 4 . digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so - si, sda/cs0 pins. (3) applied to all digital i/o pins except scl/so - si and sda/cs0 pins. downloaded from: http:///
irmcf188 16 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 5.4 analog i/o dc c haracteristics - op amp s for application sensing ( op1+, op1 - , op1 o , op2 +, op2 - , op2 o, op3 +, op3 - , op3 o) c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb - op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5 . analog i/o dc characteristics note: (1) data guaranteed by design. downloaded from: http:///
irmcf188 17 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 5.5 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 2.78 v 3.04 v 3. 2 3 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3. 2 3 v uv cc h uvcc hysteresys - 73 mv - (1) table 6 . uvcc dc characteristics note: (1) data guaranteed by design. 5.6 itrip comparator dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - v dd1 = 3.3 v itrip - itrip negative going threshold - 1.10v - v dd1 = 3.3 v itriph itrip hysteresys - 120mv - table 7 . itrip dc characteristics 5.7 cmext and aref chara cteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25?c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v vdd1 = 3.3 v v aref buffer output voltage 495 mv 600 mv 700 mv v vdd1 = 3.3 v ? v o load regulation (v dc - 0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 8 . cmext and aref dc characteristics note: (1) data guaranteed by design. downloaded from: http:///
irmcf188 18 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6 ac c haracteristics 6.1 digital pll ac c haracteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 9. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m ? r 2 =1 k ? c 1 = 15 pf c 2 = 15 pf xtal0 xtal 1 figure 6 . crystal circuit example downloaded from: http:///
irmcf188 19 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.2 analog to digital converter ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10 . a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage figure 7 . voltage droop and s/h hold time downloaded from: http:///
irmcf188 20 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.3 op amp ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/sec - vdd1 = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 - (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 11 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pf, see figure 8 . here only op - amp 1 is show n but all op amp outputs sh ould be loaded with this capacitor value . avref op1+ op1- op1o irmcf188 ic external components 47pf figure 8 op amp output capacitor downloaded from: http:///
irmcf188 21 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.4 sync to svpwm and a/d conversion ac t iming sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 9 . sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - 4, adch, adcl analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 12 . sync ac characteristics note: (1) ain 2 C ain4, adch, adcl channels are converted once every 5 sync events downloaded from: http:///
irmcf188 22 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.5 gatekill to svpwm ac t iming gatekill pwmux,pwmvx,pwmwx t wgk t dgk figure 10 . gatekill timing unless specified, ta = 25?c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 13 . gatekill to svpwm ac timing 6.6 itrip ac t iming itrip pwmuh,pwmul, pwmvh,pwmvh, pwmwh,pwmwl t itrip figure 11 . itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 14 . itrip ac timing downloaded from: http:///
irmcf188 23 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.7 i nterrupt ac t iming p3.2/int0p3.3/int1 internal program counter internal vector fetch t wint t dint figure 12 . interrupt timing unless specified, ta = 25?c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 15 . interrupt ac timing downloaded from: http:///
irmcf188 24 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.8 i 2 c ac t iming scl sda t i2st1 t i2st2 t i2wsetup t i2clk t i2whold t i2rsetup t i2rhold t i2clk t i2en1 t i2en2 figure 13 . i 2 c timing unless specified, ta = 25?c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16 . i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication. downloaded from: http:///
irmcf188 25 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.9 spi ac timing 6.9.1.1 spi write ac timing p1.3/sync/sck scl/so-si t spiclk t wrdelay t cshold sda/cs0 p3.0/int2/cs1 t cshigh bit7(msb) bit0(lsb) t spiclkht t spiclklt t csdelay figure 14 . spi write timing unless specified, ta = 25?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17 . spi write ac timing downloaded from: http:///
irmcf188 26 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.9.1.2 spi read ac timing p1.3/sync/sck scl/so-si t spiclk t rdsu t cshold sda/cs0 p3.0/int2/cs1 t cshigh bit7(msb) bit0(lsb) t spiclkht t spiclklt t csrd t rdhold figure 15 . spi read timing unless specified, ta = 25?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 18 . spi read ac timing downloaded from: http:///
irmcf188 27 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.10 uart ac t iming txd rxd data and parity bit start bit t baud stop bit t uartfil figure 16 . uart timing unless specified, ta = 25?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 19 . uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated. downloaded from: http:///
irmcf188 28 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.11 capture i nput ac t iming p1.4/cap crev(h,l) internal register t caphigh t capclk t crdelay t caplow t cldelay clast(h,l) internal register t intdelay interrupt vector fetch interrupt figure 17 . capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 20 . capture ac timing downloaded from: http:///
irmcf188 29 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.12 jtag ac t iming tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 18 . jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21 . jtag ac timing downloaded from: http:///
irmcf188 30 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 7 i/o structure the following figure shows the pwm output (pwmuh/pwmul/pwmvh/pwmvl/p wmwh/pwmwl /pfcpwm ) 270 ? 6.0v 6.0v internal digital circuit high true logic vdd1 (3.3v) vss 58k ? pin figure 19 . pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh /pfcpwm output the following figure shows the digital i/o structure except the pwm output 6.0v 6.0v internal digital circuit low true logic vdd1 (3.3v) 70k ? pin vss 270 ? figure 20 . all digital i/o except pwm output the following figure shows reset and gatekill i/o structure. downloaded from: http:///
irmcf188 31 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 270 ? 6.0v 6.0v reset gatekill circuit vdd1 (3.3v) 70k ? pin vss figure 21 . reset, gatekill i/o the following figure shows the analog input structure, except for ad cl. 1 ? 6.0v 6.0v analog input pin avss analog circuit vddcap(1.8v) figure 22 . analog input the following figure shows the adcl input structure. 1 ? 6.0v 6.0v analog input pin avss analog circuit vddcap(1.8v) 8.4 k ? 37.8 k ? vdd1 (3.3v) figure 23 . adcl pin input structure the following figure shows all analog operational amplifier output pins and aref pin i/o structure. downloaded from: http:///
irmcf188 32 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 6.0v 6.0v analog output pin avss analog circuit vddcap(1.8v) figure 24 analog operational amplifier output and aref i/o structure the following figure shows the vss,avss pin i/o structure pin vdd1 avdd 6.0v figure 25 . vss,avss pin i/o structure the following figure shows the vdd1,vddcap pin i/o structure pin vss 6.0v figure 26 . vdd1,vddcap pin i/o structure downloaded from: http:///
irmcf188 33 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 the following figure shows the xtal0 and xtal1 pins structure 1 ? 6.0v 6.0v pin vss vddcap(1.8v) figure 27 . xtal0/xtal1 pins structure downloaded from: http:///
irmcf188 34 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 8 pin list pin number pin name internal pull - up /pull - down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 4 scl/so - si i/o i 2 c clock output (open drain, need pull up) or spi data 5 sda/cs0 i/o i 2 c data (open drain, need pull up) or spi chip select 0 6 p1.3/sync/sck i/o discrete programmable i/o or sync output or spi clock output 7 p1.4/cap i/o discrete programmable i/o or capture timer input 8 p1.6 i/o discrete programmable i/o 9 p1.7 discrete programmable i/o 10 vdd1 p 3.3v digital power 11 vss p digital common 12 vddcap p internal 1.8v output, capacitor(s) to be connected 13 p2.0/nmi i/o discrete programmable i/o or non - maskable interrupt input 14 p3.2/int0 i/o discrete programmable i/o or interrupt 0 input 15 p2.2 i/o discrete programmable i/o 16 p2.3 i/o discrete programmable i/o 17 p2.6/aopwm0 i/o discrete programmable i/o or pwm 0 digital output 18 p2.7/aopwm1 i/o discrete programmable i/o or pwm 1 digital output 19 op1o o op amp output for application sensing , 0 - 1.2v range 20 op1 - i op amp negative input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 21 op1+ i op amp positive input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 22 vdcbus i analog input channel (0 C 1.2v), allocated for dc bus voltage input , needs to be pulled down to avss if unused 23 ain1 i analog input channel 1, 0 - 1.2v range, needs to be pulled down to avss if unused 24 ain2 i analog input channel 2, 0 - 1.2v range, needs to be pulled down to avss if unused 25 ain3 i analog input channel 3, 0 - 1.2v range, needs to be pulled down to avss if unused 26 ain4 i analog input channel 4, 0 - 1.2v range, needs to be pulled down to avss if unused 27 a dch i input, analog input channel dedicated for a/d compensation (0 C 1.2v) , needs to be pulled down to avss if unused 28 op2 - i op amp negative input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 29 op2+ i op amp positive input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 30 op2o o op amp output for application sensing , 0 - 1.2v range 31 cmext o unbuffered 0.6v output. capacitor needs to be connected. 32 aref o analog reference voltage output (0.6v) downloaded from: http:///
irmcf188 35 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 pin number pin name internal pull - up /pull - down pin type description 33 a dcl i input, analog input channel dedicated for a/d compensation (0 C 1.2v), internally biased to 0.6v, see figure 23 for internal structure 34 op3 - i op amp negative input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 35 op3+ i op amp positive input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 36 op3o o op amp output for application sensing , 0 - 1.2v range 37 avss p analog common 38 vddcap p internal 1.8v output, capacitor(s) to be connected 39 vdd1 p 3.3v digital power 40 vss p digital common 41 p3.1/aopwm2 i/o discrete programmable i/o or pwm 2 digital output 42 pwmwl 58 k pull down o pwm gate drive for phase w low side, configurable either high or low true. 43 pwmvl 58 k pull down o pwm gate drive for phase v low side, configurable either high or low true 44 pwmul 58 k pull down o pwm gate drive for phase u low side, configurable either high or low true 45 pwmwh 58 k pull down o pwm gate drive for phase w high side, configurable either high or low true 46 p3.7 i/o discrete programmable i/o 47 p2.1 i/o discrete programmable i/o 48 pwmvh 58 k pull down o pwm gate drive for phase v high side, configurable either high or low true 49 pwmuh 58 k pull down o pwm gate drive for phase u high side, configurable either high or low true 50 p1.5 i/o discrete programmable i/o. 51 pfcpwm i/o pfc pwm gate drive , configurable either high or low 52 pfcgkill 70 k pull up i pfcpwm shutdown input, active low input. 53 gatekill 70 k pull up i pwm shutdown input, configurable digital filter, active low input. 54 p3.0/int2/cs1 70 k pull up i/o discrete programmable i/o or external interrupt 2 input or spi chip select 1 55 p5.2/tms i jtag test mode select or digital input port 56 tdo o jtag test data output 57 p5.1/tdi i jtag test data input or digital input port 58 tck i jtag test clock 59 reset i reset, low true, schmitt trigger input 60 p1.1/rxd i/o uart receiver input or discrete programmable i/o 61 p1. 2/t xd i/o uart transmitter output or discrete programmable i/o 62 p3.4/t0 i/o discrete programmable i/o or timer/counter 2 input 63 p3.5/t1 i/o discrete programmable i/o or timer/counter 2 input 64 p3.3/int1 i/o interrupt 1 input or discrete i/o table 22 . pin list downloaded from: http:///
irmcf188 36 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 9 package dimensions downloaded from: http:///
irmcf188 37 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 10 part marking information i rmc f 188 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier 11 qualification information qualification level industrial ?? (per jedec jesd 47e) moisture sensitivity level msl3 ??? (per ipc/jedec j - std - 020c) esd machine model class b (per jedec standard jesd22 - a114d) human body model class 2 (per eia/jedec standard eia/jesd22 - a115 - a) rohs compliant yes ? qualification standards can be found at international rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please c ontact your international rectifier sales representative for further information. note: test condition for temperature cycling test is - 40c to 125c. downloaded from: http:///
irmcf188 38 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information downloaded from: http:///

▲Up To Search▲

Price & Availability of IRMCF188TY

	To Download IRMCF188TY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .